1. Technical Field
The present disclosure relates to the field of sense amplifiers for memory arrays. The present disclosure relates more particularly to the field of sense amplifiers in dual rail SRAM arrays.
2. Description of the Related Art
Memory devices typically include an array of memory cells. The array of memory cells generally includes word lines and bit lines used to select individual memory cells or groups of memory cells for reading, writing, or erasing operations. One or more sense amplifiers are typically coupled to the bit lines. The sense amplifiers amplify a voltage difference in a memory cell to aid in read processes of the memory cell.
Memory devices also include peripheral circuitry coupled to the array of memory cells. The peripheral circuitry can include control circuitry, addressing circuitry such as row and column decoders, and I/O circuitry.
In some applications it is desirable to reduce the supply voltage of the peripheral circuitry to as low a level as possible in order to reduce the power consumed by the memory device. In other devices, it is desirable to have a somewhat higher supply voltage to meet high-performance demands of the peripheral circuitry. Thus, there is a somewhat wide range of useful peripheral supply voltages depending on the specific applications of a particular memory device.
However, the memory cells of the memory array sometimes have stricter supply voltage limitations. This is because the preferred operating voltage for some memory cells is confined to a somewhat narrow range. To accommodate the needs of both the memory cells and the peripheral circuitry, memory devices often include a first supply voltage for the peripheral circuitry and a second supply voltage for the array of memory cells.
FIG. 1 is a block diagram of a known memory device 20. The memory device 20 includes an array 22 of memory cells, a bit line precharge circuit 24 coupled to the array 22, I/O circuitry 26 coupled to the array 22, decoders 28 coupled to the array 22. The memory device 20 further includes control circuitry 30 coupled to the I/O circuitry 26, decoders 28, and bit line precharge circuit 24. The bit line precharge circuit 24, I/O circuitry 26, control circuitry 30, and decoders 28 all receive a peripheral supply voltage VDDP suited to the peripheral circuitry. The memory array 22 is powered by an array supply voltage VDDA in accordance with the desired performance of the memory cells of the memory array. The array supply voltage VDDA is different from the peripheral supply voltage VDDP.
When data is to be read from or written to the array 22, the control circuitry 30 provides address data to the decoders 28. The decoders 28 decode the address data and select the correct memory cells to be read from or written to. The control circuitry 30 also controls the I/O circuitry 26 so that the proper data can be written to the memory cells or so the data can be read from the memory cells.
FIG. 2 is a schematic diagram of a portion of the array 22 of the known dual rail Static Random Access Memory (SRAM) device 20. The dual rail SRAM memory device 20 includes an SRAM memory cell 32 coupled between two bit lines BL, BLB. The bit lines BL, BLB extend between the peripheral supply voltage VDDP and the I/O circuitry 26. A sense amplifier 36 is coupled to the I/O circuitry 26 and to the bit lines BL, BLB. A sense amplifier precharge circuit 34 is coupled to the sense amplifier 36.
The memory cell 32 includes PMOS transistors P1, P2 and NMOS transistors N1-N4. Transistors P1 and N1 form a first inverter. Transistors P2, N2 form a second inverter. The gates of the transistors P1 and N1 are coupled together and comprise the input of the first inverter. The source of the transistor P1 is coupled to the array supply voltage VDDA. The source of the transistor N1 is coupled to ground. The drain terminals of the transistors P1 and N1 are coupled together and comprise the output Vout of the first inverter. The gates of the transistors P2 and N2 are coupled together and comprise the input of the second inverter. The source of the transistor P2 is coupled to the array supply voltage VDDA. The source of the transistor N2 is coupled to ground. The drain terminals of the transistors P2 and N2 are coupled together and comprise the output VoutB of the second inverter.
The first and second inverters are cross coupled together in a latch configuration such that the output Vout of the first inverter is coupled to the input of the second inverter. The output VoutB of the second inverter is coupled to the input of the first inverter. This ensures that the output Vout of the first inverter will be the logical opposite of the output VoutB of the second inverter and vice versa. Thus, if the output Vout of the first inverter is at ground, the output VoutB of the second inverter is at VDDA. If the output Vout of the first inverter is at VDDA, the output VoutB of the second inverter is at ground. The output Vout of the first inverter is coupled to the bit line BL via an access transistor N3. The output VoutB is of the second inverter is coupled to the bit line BLB via an access transistor N4. The access transistors N3 and N4 are coupled to a word line WL and are enabled when an enable signal is present on the word line WL.
The sense amplifier 36 also includes two cross coupled inverters. The first sense amplifier inverter includes the transistors P3 and N5. The second sense amplifier inverter includes the transistors P4 and N6. The output of the first sense amplifier inverter is SAout. The output of the second sense amplifier inverter is SAoutB. The first and second sense amplifier outputs are coupled to the bit lines BL and BLB via access transistors P8 and P9 and to I/O circuitry 26. The sources of the transistors N5 and N6 are coupled to ground via the access transistor N7. The transistors P8 and P9 are enabled when a sense amplifier enable signal SAen is low. The transistor N7 is enabled when the sense amplifier enable signal SAen is high.
The sense amplifier precharge circuit 34 includes three precharge transistors P5, P6, and P7 each having their gates coupled together. The source terminals in the transistors P6 and P7 are connected to VDDP. The drain terminal of the transistor P6 is coupled to the first sense amplifier output SAout. The drain terminal of the transistor P7 is coupled to the second sense amplifier output SAoutB. The transistors P5, P6, and P7 are enabled when the precharge enable signal Pch is low, forcing SAout and SAoutB to the same voltage VDDP.
An example of a read cycle of the memory cell 32 will now be provided. In this example, a binary “1” is stored in the memory cell 32. This means that the first memory cell output Vout is at VDDA while the second memory cell output VoutB is at ground.
When data is to be read from the memory cell 32, a reset phase is initiated in which both bit lines BL and BLB are precharged to the peripheral voltage VDDP by enabling the transistors N10 and N11 via the bit line enable signal BLen. During the reset phase, the precharge enable signal Pch is maintained at ground, thereby precharging SAout, SAoutB to the peripheral supply voltage VDDP. During the reset phase SAen is at ground. Thus, during the reset phase the transistors P8 and P9 are enabled while the transistor N7 is off.
After the bit lines BL, BLB and the sense amplifier outputs SAout, SAoutB are precharged to the peripheral supply voltage VDDP, the word line WL goes high and the transistors N3 and N4 are enabled. When WL goes high, Pch goes high and BLen goes low, disabling the transistors P5, P6, P7, N10, and N11. The bit lines BL, BLB and the sense amplifier outputs SAout and SAoutB are decoupled from the peripheral supply voltage source VDDP. When the word line WL first goes high, SAen is still at ground. Thus, the transistors P8 and P9 are still enabled and the transistor N7 is still off when the word line WL first goes high.
With the transistors N3 and N4 enabled, the outputs Vout, VoutB of the memory cell 32 are connected to the bit lines BL and BLB respectively. Because Vout is at the array potential VDDA, the voltage on the bit line BLB begins to increase toward VDDA. Because VoutB is at ground, the voltage on the bit line BLB begins to decrease toward ground. Because BL is coupled to SAout via the transistor P8, SAoutB begins to increase toward VDDA. Because BLB is coupled to SAoutB via transistor P9, SAoutB begins to decrease toward ground. Thus a differential voltage appears across SAout and SAoutB.
A short time after WL is enabled, SAen goes high. This disables transistors P8, P9 and enables transistor N7. With transistors P8 and P9 disabled, the sense amplifier outputs SAout and SAoutB are decoupled from the bit lines BL and BLB. The cross coupled inverters of the sense amplifier 36 comprising the transistors P3, N5 and P4, N6 are now fully enabled by being supplied with VDDP and ground voltage. The sense amplifier 36 quickly amplifies the small differential voltage between SAout and SAoutB by drawing SAoutB to ground and SAout to VDDP. Thus, the small differential voltage that appears between SAout and SAoutB when WL is enabled is amplified to the full supply voltage differential by the sense amplifier 36. The I/O circuitry 26 reads the amplified differential voltage from SAout and SAoutB thereby reading the value stored in the memory cell 32. If the value stored in the memory cell 32 had been “0”, then the sense amplifier would have brought SAout to ground and SAoutB to VDDP. The I/O circuitry 26 detects this voltage differential and reads the correct value “0” from the sense amplifier 36.
The memory device 20 of FIG. 2 suffers from some limitations. In order to keep to the array supply voltage and the peripheral supply voltage from shorting during the reset phase, the bit lines BL, BLB are precharged to the peripheral supply voltage VDDP. If the bit lines BL, BLB are precharged to the array supply voltage VDDA, then when P6, P7, P8, P9, N10, and N11 are all enabled during the reset phase, VDDA and VDDP would short-circuit and draw a very large current between VDDP and VDDA. This large current consumes a large amount of power and can damage the circuitry. Thus, the bit lines are precharged to the peripheral supply voltage VDDP to avoid this short-circuit situation.
However, if the VDDA and VDDP differ by a very large value, then when the bitlines are precharged to VDDP and the wordline is selected, data can be erroneously written to the memory cell 32 thereby corrupting the data in the memory cell 32. Thus if the bit lines are to be pre-charged to the peripheral supply voltage VDDP, constraints are placed on the value of VDDP. In other words VDDP cannot differ from VDDA by more than a relatively small amount. Thus, in an example in which the memory array 22 is powered by a relatively high voltage VDDA in order to ensure reliability, the acceptable low-end value of the peripheral supply voltage VDDP is somewhat constrained. In other words the peripheral supply voltage VDDP must be somewhat higher than a preferred value for reduced power consumption by the peripheral circuitry. Likewise, in an example in which the array supply voltage VDDA is relatively low, the acceptable high-end value of the peripheral supply voltage VDDP is somewhat constrained. In other words, the peripheral supply voltage VDDP must be somewhat lower than a preferred value for high performance requirements of the peripheral circuitry. Thus, precharging the bit lines the VDDP reduces the available range for the peripheral supply voltage VDDP.